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asahi kasei [ak8817/18] rev.001e 1 2009 / 12 ak8817/18 ntsc/pal digital video encoder general description the ak8817/18 is a digital video encoder for portable and mobile application. itu-r bt.601 level compatible y, cb,and cr signals which correspond to 27mhz or square pixel are encoded into either ntsc or pal compatible composite video signal. interface is made in hsync-, vsync- synchronized slave-m ode operation or itu-r.bt656. ak 8817/18 has 75ohm driver with lpf. it is possible to encode the vbid(cgms-a ) and wss signal on the output video signal. host control interface is i2c bus i/f. features ? ntsc-m, pal-b, d, g, h, i composite video encoding ? y:cb:cr 4:2:2 ? h/v slave operation / itu-r.bt656 interface ? y filtering: 2 x over-sampling ? c filtering: 4 x over-sampling ? 9bit dac ? setup ? macrovision rev.7.1.1l *1 ak8818 ? vbid ( cgms-a ) compatible ? wss compatible ? operation clock rate : 27mhz or square- pixel clock rate(ntsc: 24.5454mhz/pal29.50mhz) ? video amp with lpf ? on-chip color bar output ? black burst output ? power supply (avdd, dvdd) 2.7v - 3.3v ? i/f power supply (pvdd) 1.6v - 3.3v ? power down mode ? monolithic cmos ? 41pin fbga(4mm x 4mm) / 48pin lqfp (7mm x 7mm) (*2) (notice *1) this device is prot ected by u.s. patent numbers 4,631, 603, 4,577,216, and 4,819,098, and other intellectual rights. the use of ma crovision?s copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay- per -view use only, unless otherwise authorized in written by macrovision. reverse engi neering or disassembly is prohibited. (notice *2) this data sheet is compiled from package opti on devices. you will actually use, please refer to data sheet for each package.
asahi kasei [ak8817/18] rev.001e 2 2009 / 12 block diagram vref generator avdd avss dvdd dvss vref iref clkin input data control synchronization control subcarrier generator chroma lpf filter (x 2 interpolator) dacout vdi hdi sda scl rstn pdn color bar gen b.b. gen cb/cr lpf filter (x 2 interpolator) y lpf filter (x 2 interpolator) sync generato r 9-bit dac cgms d[7:0 ] u-p i/f register timing controller cb cr y v u c clk generator clkinv sin cos pvdd pvss test logic ud[4:0] test atpg vout 6db amp lpf sag
asahi kasei [ak8817/18] rev.001e 3 2009 / 12 ordering guide ak8817vg 41pin fbga ak8818vg 41pin fbga AK8817VQ 48pin lqfp ak8818vq 48pin lqfp pin assignment 1 2 3 4 5 6 7 a b c d e f g bottom view [ak8817vg pin assignment] 1 2 3 4 5 6 7 a nc dacout sag vout dvdd rstn nc b avdd avss bvss dvss pdn scl atpg c vref iref index hdi sda d ud3 ud4 pvss vdi e ud1 ud2 d0 pvdd f clkinv ud0 dvss d7 d5 d3 d1 g nc clkin dvdd d6 d4 d2 test top view [ak8818vg pin assignment] 1 2 3 4 5 6 7 a nc dacout sag vout dvdd rstn nc b avdd avss bvss dvss pdn scl atpg c vref iref index hdi sda d ud3 ud4 pvss vdi e ud1 ud2 d0 pvdd f clkinv ud0 dvss d7 d6 d3 d1 g nc clkin dvdd d5 d4 d2 test top view
asahi kasei [ak8817/18] rev.001e 4 2009 / 12 AK8817VQ / ak8818vq 1 2 34 10 6 8 9 7 51112 20 13 18 17 16 15 14 19 24 22 21 23 2726 25 30 29 28 3332 31 36 35 34 41 48 43 44 4 5 46 47 42 37 39 40 38 nc dacout avss sag bvss vout nc dvdd dvss rstn pdn at pg nc nc avd d iref vref ud4 ud3 ud2 ud1 ud0 nc nc nc clkinv clkin dvss dvdd d7 d6 d5 d4 d3 d2 nc nc scl sda hdi vdi pvss pvdd d0 d1 test nc nc AK8817VQ 1 2 34 1 0 6 8 9 7 51112 20 13 18 17 16 15 14 19 24 22 21 23 2 7 26 2 5 30 29 28 3 3 3 2 31 36 35 3 4 41 4 8 4 3 4 4 4 5 4 6 4 7 4 2 3 7 3 9 4 0 3 8 nc dacout avss sag bvss vout nc dvdd dvss rstn pdn at pg nc nc avd d iref vref ud4 ud3 ud2 ud1 ud0 nc nc nc clkinv clkin dvss dvdd d7 d6 d5 d4 d3 nc nc nc scl sda hdi vdi pvss pvdd d0 d1 test d2 nc ak8818vq
asahi kasei [ak8817/18] rev.001e 5 2009 / 12 pin functional description ak8817vg / ak8818vg ak8818 is different pin assignment from ak8817. pin# pin name i/o functional outline g2 clkin i clock input pin. input a clock which is synchronized with data. when to input 601 data : 27 mhz. when to input square pixel data : 24.5454 mhz ( ntsc )/ 29.50 mhz ( pal ) f1 clkinv i internal clock is inverted (inter nal operation timing edge is inverted.) connect to either pvdd or pvss(dgnd). b5 pdn i power down pin. after returning from pd mode to normal operation, reset sequence should be done to ak8817/18. ?l ?(gnd level): power-down ?h ?: normal operation a6 rstn i reset input pin. in order to initialize t he device , an initialization must be made in accordance with the reset sequence. ?l ? : reset ?h ? : normal operation hi-z input is acceptable to this pin at pdn = l. c7 sda i i2c data pin. this pin is pulled-up to pvdd. hi-z input is possible when pdn is at low. sda input is not accepted duri ng the reset sequence operation. b6 scl i i2c clock input pin an input level of lower-than-pvdd should be input. hi-z input is possible when pdn is at low. scl input is not accepted duri ng the reset sequence operation. f4 d7 i data video signal input pin (msb). hi-z input is acceptable to this pin at pdn = l. g4 d6 i data video signal input pin. (ak8817) hi-z input is acceptable to this pin at pdn = l. f5 d5 i data video signal input pin. (ak8817) hi-z input is acceptable to this pin at pdn = l. g4 d5 i data video signal input pin. (ak8818) hi-z input is acceptable to this pin at pdn = l. f5 d6 i data video signal input pin. (ak8818) hi-z input is acceptable to this pin at pdn = l. g5 d4 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. f6 d3 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. g6 d2 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. f7 d1 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. e6 d0 i data video signal input pin (lsb). hi-z input is acceptable to this pin at pdn = l. c6 hdi i horizontal sync signal input pin. hi-z input is acceptable to this pin at pdn = l. d7 vdi i vertical sync signal input pin. hi-z input is acceptable to this pin at pdn = l. c1 vref o on-chip vref output pin. avss level is output on this pin at pdn = l. connect this pin to analog ground via a 0.1 uf or larger capacitor. c2 iref o iref output pin. connect this pin to analog ground via a 12k ohm resistor ( better than +/- 1% accuracy ). a2 dacout o dac output pin. connect this pin to analog ground via a 390 ohm resistor ( better than +/- 1% accuracy ). a4 vout o video output pin. a3 sag i/o sag compensation input pin b1 avdd p analog power supply pin. b2 avss g analog ground pin. a5, g3 dvdd p digital power supply pin (digital core power supply). b4, f3 dvss g digital ground pin (digital core ground).
asahi kasei [ak8817/18] rev.001e 6 2009 / 12 e7 pvdd p power supply pin for chip pad. d6 pvss g ground pin for pvdd. b3 bvss g substrate ground pin. connect this pin to analog ground g7 test i for normal operation, connect to ground. b7 atpg i for normal operation, connect to ground. d2 ud4 o test output pin. fo r normal operation, left open. d1 ud3 o test output pin. fo r normal operation, left open. e2 ud2 o test output pin. fo r normal operation, left open. e1 ud1 i/o test i/o pin. for normal operation, left open. f2 ud0 i/o test i/o pin. for normal operation, left open. c3 n.c. - index pin. for normal operation, left open. a1, a7, g1 n.c. - for normal operation, left open.
asahi kasei [ak8817/18] rev.001e 7 2009 / 12 AK8817VQ/ak8818vq pin# pin name i/o functional outline 1 n.c. - for normal operation, left open. 2 n.c. - for normal operation, left open. 3 avdd p analog power supply pin. 4 iref o iref output pin. connect this pin to analog ground via a 12k ohm resistor ( better than +/- 1% accuracy ). 5 vref o on-chip vref output pin. avss level is output on this pin at pdn = l. connect this pin to analog ground via a 0.1 uf or larger capacitor. 6 ud4 o test output pin. fo r normal operation, left open. 7 ud3 o test output pin. fo r normal operation, left open. 8 ud2 o test output pin. fo r normal operation, left open. 9 ud1 o test output pin. fo r normal operation, left open. 10 ud0 o test output pin. fo r normal operation, left open. 11 n.c. - for normal operation, left open. 12 n.c. - for normal operation, left open. 13 n.c. - for normal operation, left open. 14 clkinv i internal clock is inverted (inter nal operation timing edge is inverted.) connect to either dvdd or dgnd. 15 clkin i clock input pin. input a clock which is synchronized with data. when to input 601 data : 27 mhz. when to input square pixel data : 24.5454 mhz ( ntsc )/ 29.50 mhz ( pal ) 16 dvss g digital ground pin (digital core ground). 17 dvdd p digital power supply pin (digital core power supply). 18 d7 i data video signal input pin (msb). hi-z input is acceptable to this pin at pdn = l. 19 d6 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. 20 d5 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. 21 d4 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. 22 d3 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. 23 d2 (17) n.c. (18) i ak8817: video data signal input pin. hi-z input is acceptable to this pin at pdn = l. ak8818: n.c. f or normal operation, left open. 24 n.c. - for normal operation, left open. 25 n.c. - for normal operation, left open. 26 n.c. (17) d2 (18) i ak8817: n.c. f or normal operation, left open. ak8818: video data signal input pin. hi-z input is acceptable to this pin at pdn = l. 27 test i for normal operation, connect to ground. 28 d1 i data video signal input pin. hi-z input is acceptable to this pin at pdn = l. 29 d0 i data video signal input pin (lsb). hi-z input is acceptable to this pin at pdn = l. 30 pvdd p power supply pin for chip pad.
asahi kasei [ak8817/18] rev.001e 8 2009 / 12 pin# pin name i/o functional outline 31 pvss g ground pin for pvdd. 32 vdi i vertical sync signal input pin. hi-z input is acceptable to this pin at pdn = l. 33 hdi i horizontal sync signal input pin. hi-z input is acceptable to this pin at pdn = l. 34 sda i/o i2c data pin. this pin is pulled-up to pvdd. hi-z input is possible when pdn is at low. sda input is not accepted duri ng the reset sequence operation. 35 scl i i2c clock input pin an input level of lower-than-pvdd should be input. hi-z input is possible when pdn is at low. scl input is not accepted duri ng the reset sequence operation. 36 n.c. - for normal operation, left open. 37 atpg i for normal operation, connect to ground. 38 pdn i power down pin. after returning from pd mode to normal operation, reset sequence should be done to ak8817/18vq. ?l ?(gnd level): power-down ?h ?: normal operation 39 rstn i reset input pin. in order to initialize t he device , an initialization must be made in accordance with the reset sequence. ?l ? : reset ?h ? : normal operation hi-z input is acceptable to this pin at pdn = l. 40 dvss g digital ground pin (digital core ground). 41 dvdd p digital power supply pin (digital core power supply). 42 n.c. - for normal operation, left open. 43 vout o video output pin. 44 bvss g substrate ground pin. connect this pin to analog ground 45 sag o sag compensation input pin 46 avss g analog ground pin. 47 dacout o dac output pin. connect this pin to analog ground via a 390 ohm resistor ( better than +/- 1% accuracy ). 48 n.c. - for normal operation, left open. analog output pin status mode / pin name iref vref dacout vout pdn l hi-z hi-z hi-z hi-z pdn=h dac=l videoamp=l output outpu hi-z dac power down hi-z videoamp power down pdn=h dac=h videoamp=l output output output videoamp power down(1) pdn=h dac=h videoamp=h output output output output dac: sub address 0x00 bit7 0: l->dacoff 1: h->dacon videoamp: sub address 0x01 bit3,4 00: l->videoamp_off 01,10: h-> videoamp_on note1) video amp becomes power down. since dacout pin and vout pin are c onnected with resistor in the lsi, dacout pin are not hi-z. in case of using onl y dac, vout pin and sag pin should be open states.
asahi kasei [ak8817/18] rev.001e 9 2009 / 12 electrical characteristics (1) absolute maximum ratings parameter min max units note supply voltage dvdd, avdd, pvdd -0.3 4.5 v digital input pin voltage (vinp) -0.3 pvdd +0.3 v d[7:0], hdi, vdi, rstn, pdn, clkin, clkinv,scl, sda input pin current (iin) -10 10 ma exclude power supply pin. storage temperature -40 125 c (note1) power supply voltages are values where each ground pin ( dvss = avss = pvss ) is at 0 v( voltage reference ). all power supply ground pins dvss, avss and pvss should be at same potential. (2) recommended operating conditions (2-1) ak8817vg/ak8818vg parameter min typ. max units conditions supply voltage * avdd,dvdd 2.7 3.0 3.3 v avdd = dvdd interface power supply pvdd 1.6 1.8 dvdd v operating temperature (ta) -40 85 c * power supply voltages are values where each ground pi n ( pvss = avss = pvss ) is at 0 v( voltage reference ). all power supply ground pins dvss, avss and pvss should be at same potential. (2-2) AK8817VQ/ak8818vq parameter min typ. max units conditions supply voltage * avdd,dvdd 2.7 3.0 3.6 v avdd = dvdd interface power supply pvdd 1.6 1.8 dvdd v operating temperature (ta) -40 105 c * power supply voltages are values where each ground pi n ( pvss = avss = pvss ) is at 0 v( voltage reference ). all power supply ground pins dvss, avss and pvss should be at same potential.
asahi kasei [ak8817/18] rev.001e 10 2009 / 12 (3) dc characteristics (3-1) ak8817vg / ak8818vg < operating voltage: dvdd 2.7v~3.3 v / pvdd 1.6 v~dvdd, loading condi tion 15 pf, temperature -40~+85 c > parameter symbol min typ max units conditions digital input h voltage (vih) vih 0.8pvdd v pvdd=1.6 - dvdd digital input l voltage (vil) vi l 0.2pvdd v pvdd=1.6 - dvdd digital input leak current il +/-10 ua i2c (sda) l output volc 0.4 v iolc = 3ma ( note ) digital output pins refer to d[7:0], hdi, vdi, pdn, rstn, scl, sda,clkin and clkinv pin outputs in general term. (3-2) AK8817VQ / ak8818vq < operating voltage: dvdd 2.7v~3.6 v / pvdd 1.6 v~dvdd, loading condi tion 15 pf, temperature -40~+105 c > parameter symbol min typ max units conditions digital input h voltage (vih) vih 0.7pvdd 0.8pvdd v 2.7v Q pvdd Q dvdd 1.6v Q pvdd 2.7v digital input l voltage (vil) vil 0.3pvdd 0.2pvdd v 2.7v Q pvdd Q dvdd 1.6v Q pvdd 2.7v digital input leak current il +/-10 ua i2c (sda) l output volc 0.4 v iolc = 3ma ( note ) digital output pins refer to d[7:0], hdi, vdi, pdn, rstn, scl, sda,clkin and clkinv pin outputs in general term.
asahi kasei [ak8817/18] rev.001e 11 2009 / 12 (4) analog characteristics ak8817vg / ak8818vg < avdd = 3.0 v, temperature 25 c > AK8817VQ / ak8818vq < avdd = 3.3 v, temperature 25 c > parameter symbol min typ max units dac resolution 9 bit dac integral non-linearity ( error ) +/- 0.6 +/- 2.0 lsb dac differential non-linearity ( error ) +/- 0.4 +/- 1.0 lsb dac output full scale volt age 1.18 1.28 1.38 v note1) dac output offset volt age 5.0 mv note2) video amp output gain 5.0 6.0 7.0 db amp input level 1vpp video amp full scale level 2.0 vpp note3) video amp thd -45 -51 db 100khz - 5.5mhz note4) video amp s/n 54 db 100khz - 5.5mhz note4) lpf ripple -1 +/- 0.5 +1 db 100khz - 5.5mhz 0db = 100khz input lpf stop band level 20 30 db 27mhz 0db = 100khz input lpf group delay 10 100 ns |gd3mhz - gd6mhz| on-chip reference voltage (vref) 1.17 1.23 1.30 v reference voltage drift -50 ppm/ c note1) values are when a 390 ohm out put load, a 12k ohm iref pin resi stor and on-chip vref are used. full scale output current is calculated as iout = full scale output voltage ( ty p. 1.28 v ) / 390 ohm = typ. 3.28 ma. note2) a voltage referenced to vss when a dec imal zero voltage is input to dac. note3) vout output level out put load resistor: 150ohm, load capacitor: 15pf internal color bar output note4) output signal from dac to which input dat a corresponded 1vpp. this signal is input to amp. load resistor is 150ohm and load capacitor is 15pf as shown bellow figure at (5 ) current consumption.
asahi kasei [ak8817/18] rev.001e 12 2009 / 12 (5) current consumption (5-1) ak8817vg / ak8818vg < operating voltage : dvdd = av dd = pvdd = 3.0 v, ta = +25 c > parameter symbol min typ max units total power consumption 27 35 ma note1) power-down current 1 10 30 ua note2) digital part operating curr ent 1 13 ma note3) analog part operating current 1 14 ma note4) analog part operating current 2 5.5 ma note5) analog part operating current 3 0.8 ma note6) (5-1) AK8817VQ / ak8818vq < operating voltage : dvdd = av dd = pvdd = 3.3 v, ta = +25 c > parameter symbol min typ max units total power consumption 29 38 ma note1) power-down current 1 10 30 ua note2) digital part operating curr ent 1 13 ma note3) analog part operating current 1 14 ma note4) analog part operating current 2 5.5 ma note5) analog part operating current 3 0.8 ma note6) note1) operation at 27 mhz, ntsc m ode on-chip 75% color bar output is enabl ed and video amp output is ? on ? ( no external output loads are c onnected except for recommended co mponents. ). 15pf capacitors in following figure represent pcb layout-capacitor. sag compensation on sag compensation off 75ohm ak8817 vout sag 75ohm 100uf 15pf ak8817 vou t sag 47uf 1uf 75ohm 75ohm 15pf 15pf 15pf note2) measuring conditions : input / output settings after power-down sequence are, pdn pin is at gnd level, clkout and sdo output are at high level ( power supply voltage ) with no external connection, input voltage on those input pins is 1/2 level of power supply which are set to accept hi-z input at power- down, and test = atpg = gnd ( or left open ). power supplies are avdd = dvss = pvdd. each ground pin ( dvss, avss, pvss ) is always 0 v ( voltage reference ). note3) operation at 27 mh z, ntsc mode on-chip 75% color bar output is enabled. note4) dac on, video amp on sag compensation on note5) dac on, video amp off (sag compensation off) note6) dac off, video amp off (sag compensation off)
asahi kasei [ak8817/18] rev.001e 13 2009 / 12 ac timing loading condition : cl = 15 pf ak8817vg / ak8818vg < dvdd 2.7 v ~ 3.3 v / pvdd 1.6 v ~ dvdd, ta at -40 ~ +85 c > AK8817VQ / ak8818vq < dvdd 2.7 v ~ 3.3 v / pvdd 1.6 v ~ dvdd, ta at -40 ~ +105 c > (1) clk clkin fclki tclkih tclkil vil vih 1/2 pvdd parameter symbol min. typ. max unit conditions 24.5454 pixrt=1 ntsc 27 pixrt=0 ntsc/pa clkin fclki 29.50 mhz pixrt=1 pal clk duty ratio pclkid 40 60 % clk accuracy 100 ppm tclkil, tclkih : minimum pulse width 12 ns ( tr/tf10%-90%level rising/falling time 2ns)
asahi kasei [ak8817/18] rev.001e 14 2009 / 12 (2) pixel data input timing tds tdh d[7:0] hdi vdi clkin vih vil clkinv = low parameter symbol min. typ. max unit conditions data setup time tds 5 nsec data hold time tdh 8 nsec when clkinv = high, similar tds and tdh ar e specified at the falling edge of clkout. (3) hsync pulse width hsync p hsw parameter symbol min. typ. max unit conditions 15 116 ntsc (24.5454mhz) 15 128 27mhz hdi pulse width phsw 15 139 clks pal (29.50mhz) * typical values are calculated by converting the hsync pulse width of analog video specificat ion into number of system clock pulses.
asahi kasei [ak8817/18] rev.001e 15 2009 / 12 (4) reset (4-1) reset timing rstn pres clkin 1 2 99 100 parameter symbol min. typ. max unit rstn pulse width pres 100 clks (4-2) power down sequence / reset sequence before pdn setting ( pdn to low ), reset must be enabled for a duration of longer-than-100 clock time. after pdn release ( pdn to high ), reset must be enabled for 10 ms or longer till analog part reference voltage & current are stabilized. vil vih rstn pdn clkin hres sres vih (clkout=h) gnd parameter symbol min. typ. max unit rstn pulse width sres 100 clks time from pdn to high to rstn to high hres 10 msec scl low duration before rstn to rise tscll 50 nsec at power-down, all control signals must be surely connected to either the se lected power supply or ground level, and not to vih / vil levels.
asahi kasei [ak8817/18] rev.001e 16 2009 / 12 (4-3) power down sequence/power up sequence a vdd/dvdd pvdd pdn rstn vref 10ms(min) recover from power down state (4-4) power on reset after power up, it is necessary to make reset sequence until analog reference voltage(vref) becomes stable. pvdd/dvdd/avdd should be power up at same time or 1st pvdd power up and avdd/dvdd makes up. rstn 0.2pvdd avdd dvdd 2.7v pvdd 1.6v vref pdn 10ms ( min ) 0.8pvdd item symbol min typ max unit note resetn pulse width pres_pon 10 msec remark: reset sequence requires clock input.
asahi kasei [ak8817/18] rev.001e 17 2009 / 12 (5) i2c bus input/output timing < ta = -30 ~ +85 c > (5-1) timing 1 vsdah: 0.8pvdd vsdal : 0.2pvdd parameter symbol min. max. unit bus free time tbuf 1.3 usec hold time (start condition) thd:sta 0.6 usec clock pulse low time tlow 1.3 usec input signal rise time tr 300 nsec input signal fall time tf 300 nsec setup time(start condition) tsu:sta 0.6 usec setup time(stop condition) tsu:sto 0.6 usec the above i2c bus related timing is specified by the i2c bus specification, and it is not limited by the device performance. for details, please refe r to the i2c bus specification. (5-2) timing 2 sda thd:dat thigh tsu : dat scl vsdah vsdal vsdah vsdal vsdah: 0.8pvdd vsdal : 0.2pvdd parameter symbol min. max. unit data setup time tsu:dat 100 (note1) nsec data hold time thd:da t 0.0 0.9 (note2) usec clock pulse high time thigh 0.6 usec note 1 : when to use i2c bus standard m ode, tsu:dat >- 250 ns must be met. note 2 : when the ak8817/18 is used in such bus interface where tlow is not ex tended ( at minimum specification of tlow ), this condition must be met. tr tlow sda tbuf thd : sta tf tr tf tsu : sto tsu : sta scl vsdah vsdal vsdah vsdal
asahi kasei [ak8817/18] rev.001e 18 2009 / 12 device control interface the ak8817/18 is controlled via i2c bus control interface. [ i2c slave address ] 2c slave address is 0x40 [ i2c control sequence ] (1) write sequence when the slave address of the ak8817/18 write mode is received at the first byte, sub address at the second byte and data at the third and succeeding bytes are received. there are 2 operations in write sequence - a sequence to write at every single by te, and a sequential write operation to write multiple bytes successively. (a) 1 byte write sequence s slave address w a sub address a data a stp 8-bits 1bit 8-bits 1bit 8-bits 1bit (b) multiple bytes ( m-bytes ) write sequence ( sequential write operation ) s slave address w a sub address (n) a data(n) a data(n+ 1) a data(n+m) a stp 8-bits 1bit 8-bits 1bit 8-bits 1bit 8-bits 1bit ?. 8-bits 1bit (2) read sequence when the slave address of the ak8817/ 18 read mode is received, data at the second and succeeding bytes are transmitted. s slave address w a sub address (n) a rs slave address ra data1 a data2 a data3 a ? data n stp 8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1 8-bits 1 abbreviated terms listed above mean : s, rs : start condition a : acknowledge ( sda low ) a- : not acknowledge ( sda high ) stp : stop condition r/w 1 : read 0 : write : to be controlled by the master device. micro-computer interface is output normally . : to be controlled by the slave device. to be output by the ak8817/18.
asahi kasei [ak8817/18] rev.001e 19 2009 / 12 video encoder functional outline (1) reset (1-1) reset of serial interf ace part ( asynchronous reset ) reset is made by setting rstn pin to low. (1-2) reset of other than serial interface blocks reset is made by keeping rstn pin low for a longer than 100 clock time, in normal operation. (1-3) at power-on-reset ( including power-down release case ) follow the power-on-reset sequence. at the completion of each initializ ation, all internal registers are set to default values ( refer to register map ). right aft er the reset, video output of the ak8817/ 18 is put into hi-z condition. (2) power-down it is possible to put the device into power-down m ode by setting the ak8817/18 power-down pin to gnd. transition to power-down mode should be followed by the power-down sequence. as for the recover from the power-down mode, it should be followed by the power-down release sequence. (3) master clock a following clock should be input as a master clock. in encoder mode operation ( a synchroniz ed clock with input data is required ) when itu-r bt.601 data is input ( pixrt-bit = 0 ) when square pixel data is input ( pixrt-bit = 1 ) ntsc encoder 27mhz 24.5454mhz pal encoder 27mhz 29.50mhz (4) video signal interface video input signal ( data ) should be synchroniz ed in either of the following methods : * slave mode operation where synchronization is made with hsync ( hdi ) / vsync ( vdi ). * itu-r bt. 656 i / f ( eav decode ) (only 27mhz operation) (5) pixel data input data to the ak8817/18 is ycbcr ( 4:2:2 ). data with y : 16 ~ 235 and cbcr : 16 ~ 240 should be input. (6) video signal conversion video re-composition module converts t he multiplexed data ( itu-r bt.601 level y, cb, cr ) into interlaced ntsc-m and pal-b, d, g, h, i data. video encoding setting is done by ?control 1 register ?.
asahi kasei [ak8817/18] rev.001e 20 2009 / 12 (7) luminance signal filter ( luma filter ) luminance signal is output via lpf ( see x2 luma filter in the block diagram ). -50 -40 -30 -20 -10 0 10 0 . 0 1 . 0 2 . 0 3 . 0 4 . 0 5 . 0 6 . 0 7 . 0 8 . 0 9 . 0 1 0 . 0 1 1 . 0 1 2 . 0 1 3 . 0 frequency[mhz] gain[db] (8) chroma signal filter ( chroma filter ) chroma input signal components ( cb, cr ) prior to t he modulation go through a 1.3 mhz band limiting filter ( see 4:2:2 to 4:4:4 x2 inter polator in the block diagram ). chroma signal which is modulated by the s ub-carrier is output via a low pass filter ( chroma lpf in the block diagram ). frequency response of each f ilter is shown below. 4:2:2 to 4:4:4 inte rpolator filter -50 -40 -30 -20 -10 0 10 0.00.51.01.52.02.53.03.54.04.55.05.56.06.5 frequency[mhz] gain[db] x 2 interpolator filter -50 -40 -30 -20 -10 0 10 0 . 0 1 . 0 2 . 0 3 . 0 4 . 0 5 . 0 6 . 0 7 . 0 8 . 0 9 . 0 1 0 . 0 1 1 . 0 1 2 . 0 1 3 . 0 frequency[mhz] gain[db]
asahi kasei [ak8817/18] rev.001e 21 2009 / 12 (9) color burst signal burst signal is generated by a 32 bit digital frequency synthesizer. color burst frequency is selected by mode setting of ntsc / pal. standerd subcarrier freq (mhz) video process 1 vmod-bit ntsc-m 3.57954545 0 pal-b,d,g,h,i 4.43361875 1 burst signal table (10) sub - carrier reset a function to reset sub-carrier by color frame sequence. reset function can be turned ?off ? by se tting scr-bit of control 1 register. default value is set to enable sub-carrier reset. scr 0 1 ntsc sub-carrier phase is reset in every 2 frames ( 4 fields ) sub-carrier reset is not done pal sub-carrier phase is reset inevery 4 frames ( 8 fields ) sub-carrier reset is not done (11) setup processing setup processing can be performed on video si gnal by control 2 register setup-bit. following processing is made on luminance signal ( y signal ) and chroma signal ( c signal ) by the setup processing. y setup = y x 0.925 + 7.5 ire where y setup is the luminance signal after setup processing. c setup = c x 0.925 where c setup is t he chroma signal after setup processing. (12) video dac the ak8817/18 has a 9 bit resolution, current-drive dac as a video dac which runs at 29. 5 / 24.5454 mhz or 27.00mhz clock frequency. this dac is designed to output 1.28 v o- p at full scale under the following condi tions loading resistance of 390 ohms, vref at 1.23 v and iref pin resistor of 12k ohms. [ vref ] pin should be connected to ground via a 0.1 uf or larger capacitor. dac output can be turned ?on? or ?o ff? by register setting and current consumption can be lowered. when the output is turned off, it is put into high impedance condition.
asahi kasei [ak8817/18] rev.001e 22 2009 / 12 (13) video amp ak8817/18 has video amp that can drive 150ohm with low pass filter. it can also possible to compensate sag distortion. to compensate sag external capacitor is 47uf and 1uf as shown following fi gure. recommendation voltage when sag compensation circuit is used is 3v or more. vout pin and sag pin should be shorten when sag compensation is not used. ou tput pin should make ac coupling. sag compensation circuit can be set on or off with setting register. in case of not using internal video amp (only dac use ca se), video amp becomes power down. in this case sag and vout should be open. ak8817 vou t sag 47uf 1uf 75ohm sag compensation on ak8817 vout sag 75ohm sag compensation off 100uf vampmd[1:0] operation conditions 00 video amp off + sag compens ation off only dac output 01 video amp on + sag compensation on recommendation voltage of dvdd/avdd is 3v or more. 10 video amp on + no sag compensation sag pin and vout should be shorten. 11 reserved
asahi kasei [ak8817/18] rev.001e 23 2009 / 12 (14) video data interface timing data is captured by a clock which is fed on clkin pin. the video encoder receives a clock from a cont roller ( refer to the following diagram ). in slave mode operation, synchronization is made with hdi / vdi. in itu-r bt.656 mode operation, hdi / vdi are not required. controller ak8817 clkin (h d i) (v d i) d[7:0]
asahi kasei [ak8817/18] rev.001e 24 2009 / 12 (14-2) video interface mode the ak8817/18 synchronizes with input signal by the following, 2 interface modes. (a) slave-mode interface where synchronization is made with externally-fed synchronization signals hdi / vdi ( hdi / vdi interface ) (b) itu-r bt.656 interface mode ( 656 interface ) interface mode setting is controlled by [rec656]-bit of control 2 register. rec656-bit operation 0 hdi / vdi slave mode 1 itu-r bt.656 interface mode (a-1) timing signal ( hdi / vdi ) vs data input relation horizontal synchronization ( in-line pixel sync ) is made with hdi synchronization timing signal. vertical synchronization ( in-line frame line sync ) is made with vdi synchronization timing signal. recognition of video field ( odd field or even field ) is made by vdi input signal which is referenced with hdi. in normal operation, the ak8817/18 c hecks changes of hdi and vdi at the clock edge ( clk synchronization ) which becomes a data captur e reference position. at a pixel position where hdi is judged to become ? low ?, it is recognized as 0 h (zero th position ). cb0 data position depends on input data rate ( itu-r bt.601 or square pixel data ). cb0 data at itu-r bt.601 data input at square pixel data input ntsc encoder 244 th data 236 th data pal encoder 264 th data 310 th data video field is recognized by the vdi relation with hdi. field recognition is made as follows : the ak8817/18 distinguishes at every field if it is odd field ( 1 st field ) or not. even field sync signal is not usually input. 1 ) recognition timing of odd field is decided by those ti ming signal relations which are fed on hdi and vdi pins. when the vdi falling pulse is input on vdi input pin during the time from 3 clocks prior to the falling edge of hdi timing pulse which is fed on hdi input till 3 clocks prior to the rising edge of hdi timing pulse, the line is recognized to be line 4. hdi line4/line1(ntsc/pal) line5/line2(ntsc/pal) vdi 3clk 3clk line6/line3(ntsc/pal) 2 ) whenever horizontal / vertical sync signal inputs are not fed as expected in the video specifications, in term of timing and # of pulses ( kept at ? high ? level ), the ak8817/18 continues to se lf-run the operation wh ich is based on the sync signals, fed just before. but it is recommended to feed sync signals as specifi ed every time in order to prevent erroneous operation. 3 ) vd pulse input at other than odd field synchronization is ignored ( synchronization is made with odd field only ).
asahi kasei [ak8817/18] rev.001e 25 2009 / 12 (a-2) horizontal synchronization ( pixe l data synchronization within a line ) (a-2-1) at itu-r bt. 601 data input case (a-2-1-1) ntsc clkin (27.00mhz) dti[7:0] cb0 y0 cr0 y1 cb1 cr359 y719 hdi 720 x 2 clock active video area (0x80) (0x10) (0x80) (0x10) (0x80) (0x10) (0x10) 0 h 1715 0 244 245 246 247 248 1684 1683 244t (0x10) 1713 (0x80) 1714 * ) when d [7:0], hdi and clkin are in same phase relation as a timing example above, the ak8817/18 takes input data at the falling edge of each clkin if clkedge-bit = 1.(clkinv = 1.) * ) as an input data other than during acti ve video period, black level ( c / y = 0x80 / 0x10 ) or other than 0x00 / 0xff codes in non hi-z state should be input. (a-2-1-2) pal clkin (27.00mhz) dti[7:0] cb0 y0 cr0 y1 cb1 cr359 y719 hdi 720 x 2 clock active video area (0x80) (0x10) (0x80) (0x10) (0x80) (0x10) (0x10) h0 1727 0 264 265 266 267 268 1704 1703 1702 264t (0x10) 1725 (0x80) 1726 *) when d [7:0], hdi and clkin are in same phase relation as a timing example above, the ak8817/18 takes input data at the falling edge of each clkin if clked ge-bit = 1. .( clkinv = 1.) * ) as an input data other than during acti ve video period, black level ( c / y = 0x80 / 0x10 ) or other than 0x00 / 0xff codes in non hi-z state should be input.
asahi kasei [ak8817/18] rev.001e 26 2009 / 12 (a-2-2) at square pixel rate input case (a-2-2-1) ntsc clkin (24.5454mhz) d[7:0] cb0 y0 cr0 y1 cb1 cr319 y639 hdi 640 x 2 clock active video area (0x80) (0x10) (0x80) (0x10) (0x80) (0x10) (0x10) h0 1559 0 tbd 236 237 238 239 240 1516 1515 1514 * ) when d [7:0], hdi and clkin are in same phase relation as a timing example above, the ak8817/18 takes input data at the falling edge of each cl kin if clkinv = 1. * ) as an input data other than during acti ve video period, black level ( c / y = 0x80 / 0x10 ) or other than 0x00 / 0xff codes in non hi-z state should be input. (a-2-2-2) pal clkin (29.5mhz) d[7:0] cb0 y0 cr0 y1 cb1 cr383 y767 hdi 768 x 2 clock active video area (0x80) (0x10) (0x80) (0x10) (0x80) (0x10) (0x10) h0 1887 0 tbd 310 311 312 313 314 1844 1845 1846 * ) when d [7:0], hdi and clkin are in same phase relation as a timing example above, the ak8817/18 takes input data at the falling edge of each clkin if clki nv-bit = 1. .(clkinv = 1.) * ) as an input data other than during acti ve video period, black level ( c / y = 0x80 / 0x10 ) or other than 0x00 / 0xff codes in non hi-z state should be input.
asahi kasei [ak8817/18] rev.001e 27 2009 / 12 ( a-3 ) hdi and vdi relation in each frame ( a-3-1 ) ntsc ( frame ) 525 line 480 active lines the first field ( odd ) hdi vdi 4 5 6 7 22 23 3 1 525 2 261 262 263 264 240 lines 263 lines * )vdi negative-going should be fed during the time from 3 clocks prior to negative-going of hdi at l4 till 3 clocks prior to positive-going of hdi. vdi positive-going can occurs at arbitrary location, but keep vdi low for 3 line duration time as a rough idea. the second field ( even ) hdi vdi 267 268 269 270 285 286 266 264 263 265 524 525 1 2 240 lines high 262 lines * ) vdi negative-going is not required for t he second field. it is required for the fi rst field only ( vdi fed during the secon d field is ignored ).
asahi kasei [ak8817/18] rev.001e 28 2009 / 12 ( a-3-2 ) pal ( frame ) 625 line 576 active lines the first field ( odd ) hdi vdi 4 5 22 23 24 3 1 625 2 310 311 312 313 288lines 313lines 314 * ) vdi negative-going should be fed during the time from 3 clocks prior to negative-going of hdi at l1 till 3 clocks prior to positive-going of hdi. vdi positive-going can occur at arbitrary lo cation, but as a rough idea, keep vdi low fo r 2.5, or 2 or 3 line- duration time. data fed at line 23 is not output on video output the second field (even) hdi vdi 317 318 335 336 337 316 314 313 315 623 624 625 1 288lines 313lines 2 high *) vdi negative-going is not required for t he second field. it is required for the fi rst field only ( vdi fed during the second field is ignored ). data fed at line 623 is not output.
asahi kasei [ak8817/18] rev.001e 29 2009 / 12 ( b-1 ) itu-r bt.656 interface mode the ak8817/18 makes a synchronization with an incoming signal by decoding eav in the signal when itu-r bt.656 encoded signal is input. eav code is located at the following positi on in the video stream ( this mode of oper ation is not support ed in the square pixel clock operation ). eav sav y/ cb/ cr cb y cr y cb y cr y cb y cr y cb y cr y cb y cr y cb data# 525 system 360 720 360 721 361 722 361 723 368 736 368 855 428 856 428 857 0 0 0 1 1 data# 625 system 360 720 360 721 361 722 361 723 366 732 366 861 431 862 431 863 0 0 0 1 1 33 / 25t (525 / 625) 243 / 263t (525 / 625) clki n hdi 276/ 288t (525 / 625)
asahi kasei [ak8817/18] rev.001e 30 2009 / 12 ( 1 ) eav synchronization an eav code which is encoded on input signal is decoded, and t he device makes synchronization with its timing. eav / sav codes are as follows. those codes succeeding 0xff- 0x00- 0x00 which are fed as input data in 8-bit form become eav / sav codes. eav / sav codes have following meanings, starting with msb. bit number msb lsb word value 7 6 5 4 3 2 1 0 0 0xff 1 1 1 1 1 1 1 1 1 0x00 0 0 0 0 0 0 0 0 2 0x00 0 0 0 0 0 0 0 0 3 0xxx 1 f v h p3 p2 p1 p0 here, f = 0 : field 1 = 1 : field 2 v = 0 : other than filed blanking (v-blanking) = 1 : filed blanking (v-blanking) h = 0 : sav = 1 : eav p3, p2, p1, p0 : protection bit protection bit and f / v / h relation is shown in the following table. f v h p3 p2 p1 p0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 at ntsc data input case cb y cr y cb y cr y cb y cr y cb y cr y 359 718 359 719 360 720 360 721 428 856 428 857 0 0 0 1 eav ?? sav at pal data input case cb y cr y cb y cr y cb y cr y cb y cr y 359 718 359 719 360 720 360 721 431 862 431 863 0 0 0 1 eav ?? sav
asahi kasei [ak8817/18] rev.001e 31 2009 / 12 ( 1-1 ) eav / sav code and line synchronization the ak8817/18 makes vertical synchronization ( line synchr onization ) when f-bit in eav makes transition from ? 1 ? to ? 0 ?. f-bit of eav / sav and line relation is as follows f-bit ntsc pal 0 line4 ? line265 line1 ? line312 1 line266 ? line525 line1 ? line3 line313 ? line625 for reference, v-bit of eav / sav and line relation is also shown below. field v-bit ntsc pal start (v=1) line1 ? line19 line624 ? line625 ? line22 field 1 end (v=0) line20 ? line263 line23 ? line310 start (v=1) line264 ? line282 line311 ? line335 field 2 end (v=0) line283 ? line525 line336 ? line623 digital line-no. f-bit 267 268 269 270 271 272 266 digital line-no. f-bit 4 5 6 7 8 9 3 2 1 265 264 263 line synchronization by eav at ntsc input case synchronization is made at this timing digital line-no. f-bit 314 315 316 317 318 319 313 digital line-no. f-bit 1 2 3 4 5 6 625 624 623 312 311 310 line synchronization by eav at pal input 622 synchronization is made at this timing
asahi kasei [ak8817/18] rev.001e 32 2009 / 12 (15) on-chip color bar the ak8817/18 can output color bar signal. color bar signal to be generated has 100 % amplitude and 75 % saturation levels. color bar signal is output by setting register. when to output color bar signal, there are 2 modes of operation ? one is exte rnal sync timing mode for normal operation, and the other is in ternal self-operation mode. in internal self-operating mode, requir ed timing is internally generated automatic ally. namely, it is no need to input synchronization timing from outside of the chip. operation mode setting is done by control 1 register . when bbg-bit is set, bbg-bit is prioritized ( black burst is output ). blanking level 100%white synctip level white yellow cyan green magenta red blue black the following values are code for itu-r. bt601 white yellow cyan green magenta red blue black cb 128 44 156 72 184 100 212 128 y 235 162 131 112 84 65 35 16 cr 128 142 44 58 198 212 114 128 (16) black burst signal generation function the ak8817/18 can output black burst signal ( black level output ). when to output black burst signal, there are 2 modes of operation ? one is external sync timing mode for normal operation , and the other is in ternal self-operation mode. in internal self-operation mode, requir ed timing is internally generated automatic ally. namely, it is no need to input synchronization timing from outside of the chip. when bbg-bit of [ control 1 register ] is set to ?1?, same operation is processed as in t he case where fixed-16 y signal and fixed-128 cb / cr signal outputs are input. operation mode setting is done by control 1 register setting.
asahi kasei [ak8817/18] rev.001e 33 2009 / 12 (17) video id the ak8817/18 supports to encode the video id ( eiaj cp r-1204 ) which distinguishes the aspect ratio etc.. this is also used as cgms ( c opy generation managem ent system ). turning ?on/off? of this function is made by setting both vmod-bit = 0 and vbid-bit = 1 of { control 1 register (0x00) }. and data to be set is written into { vbid / wss data1 & 2 registers ( 0x02,0x03 )}. video id information is the highest order of priority information among vbi information vbid data update timing . vsync new data data old data new data u-p data set control register vbid code assignment 20 bit data is configured with word0 = 2 bit, word1 = 4 bit, word2 = 8 bit and crc = 6 bit. crc is automatically calcul ated and added by the ak8817/18. default values of crc polynomial expression x6 + x + 1 are all ones. -data configuration bit1 bit20 data word0 2bit word1 4bit word2 8bit crc 6bit vbid waveform ref. bit1 bit2 bit3 bit20 ??? 2.235usec +/- 50nsec 11.2usec +/- 0.3usec 49.1usec +/- 0.44usec 1h 70ire +/- 10ire 0ire + 10 ire ? 5 ire 525/60 system amplitude 70ire encode line 20/283
asahi kasei [ak8817/18] rev.001e 34 2009 / 12 ( 17 ) wss function the ak8817/18 supports to encode the wss ( itu-r. bt .1119 ) which distinguishes the aspect ratio and sets cgms-a etc.. turning ?on/off? of this function is made by setting both vmod-bit = 1 and wss-bit = 1 of { control 1 register ( 0x00 ) }. and data to be set is written into { vbid / wss data1 & 2 registers ( 0x02, 0x03 )}. wss data update timing vsync new data data old data new data u-p data set control register wss waveform 10.5usec 27.4usec 38.4usec 500mv +/- 5% 11.0 +/- 0.25usec 44.5usec 1.5usec 0 h encode line : former half of line 23 ( blank output during latter half ) coding : bi-phase modulation coding clock : 5 mhz ( ts = 200 ns ) encoding details as follows run-in start code group 1 aspect ratio group 2 enhanced services group 3 subtitles group4 reserved 29 elements 24 elements 24 elements 24 elements 18 elements 18 elements bit numbering 0 1 2 3 lsb msb 0 : 000111 1 : 111000 bit numbering 4 5 6 7 lsb msb 0 : 000111 1 : 111000 bit numbering 8 9 10 lsb msb 0 : 000111 1 : 111000 bit numbering 11 12 13 lsb msb 0 : 000111 1 : 111000 0x1f1c71c7 0x1e3c1f
asahi kasei [ak8817/18] rev.001e 35 2009 / 12 sync signal waveform, burst waveform generator (1) ntsc-j 90% 50% 10% 50% sync rise time sync horizontal reference point 50% sync level 50% h . ref. to b urst start burst height burst measurement point value consumer quality tolerance units total line period(derived) 63.556 usec sync level 40 +/- 3 ire sync rise time 10% - 90% 140 max 250 nsec horizontal sync width 50% 4.7 +/- 0.1 usec horizontal reference point to burst start 50% 19 defined by sc/h cycles burst * 50% 9 +/- 1 cycles burst height ** 40 +/- 3 ire * there is a case where tolerance of sync rise time is added to sync width tolerance. * measurement of burst ti me length is made between the burst start point which is defined as the zero-cross point, preceding the first half-cycle of the sub-carrier w here burst amplitude becomes higher than 50 % level and the burst end point , defined in the same manner. 9 cycles +/- 1cycle 19 cycles +/-10 50% ntsc signal
asahi kasei [ak8817/18] rev.001e 36 2009 / 12 (2) vertical sync signal timing ( ntsc ) 3h 3h 1 2 3 4 5 6 7 89 0.5h 3h 3h 3h 263 264 0.5h 3h 265 266 267 268 269 270 271 272 273 21 285 equalizing pulse and serration pulse equalizing pulse serration pulse g h 40ire i i i i +/-3ire symbol measurement point value recommended tolerance units g pre-equalizing pulse width 50% 2.3 +/- 0.1 usec h vertical serration pulse width 50% 4.7 +/- 0.2 usec g post-equalizing pulse width 50% 2.3 +/- 0.1 usec i sync rise time 140 max 250 nsec * there is a case where tolerance of sync rise time is added to pulse width tolerance.
asahi kasei [ak8817/18] rev.001e 37 2009 / 12 (3) pal-b,d,g,h,i 90% 50% 10% 50% sync rise time horizontal sync horizontal reference point 50% sync level 50% h . ref. to b urst start burst height burst measurement point value consumer quality tolerance units total line period(derived) 64.0 usec sync level 300 +/- 20 mv sync rise time 10% - 90% 0.2 max 0.3 usec horizontal sync width 50% 4.7 +/- 0.2 usec horizontal reference point to burst start 50% 5.6 +/- 0.1 usec burst * 50% 10 +/- 1 cycles burst height ** 300 +/- 30 mv * there is case where tolerance of sync ri se time is added to sync width tolerance.
asahi kasei [ak8817/18] rev.001e 38 2009 / 12 (4) vertical sync signal timing and burst phase pal-b,d,g,h,i 313 314 315 316 317 318 320 319 321 322 311 312 310 309 308 a b 313 314 315 316 317 318 320 319 321 322 311 312 310 309 308 a b a b 623 624 625 123 4 56 8 7 622 621 620 a b 623 624 625 123 4 56 8 7 622 621 620 a : phase of burst : nominal value + 135 b : phase of burst : nominal value - 135 since burst frequency and line frequency are not practically in in teger-multiple relation, spec ified phase value is not exactly 135 degrees. diagram below shows phase direction. equalizing pulse and serration pulse equalizing pulse serration pulse g h 300mv i i i i +/-30mv symbol measurement point value recommended tolerance units g pre-equalizing pulse width 50% 2.35 +/- 0.1 usec h vertical serration pulse width 50% 4.7 +/- 0.2 usec g post-equalizing pulse width 50% 2.35 +/- 0.1 usec i sync rise time 200 max 300 nsec * there is a case where tolerance of sync rise time is added to pulse width tolerance.
asahi kasei [ak8817/18] rev.001e 39 2009 / 12 register map address register default r/w function 0x00 control 1 register 0x00 r/w mode set register 0x01 control 2 register 0x00 r/w mode set register 0x02 vbid/wss data 1 register 0x00 r/ w vbid data is set, wss data is set 0x03 vbid/wss data 2 register 0x00 r/ w vbid data is set, wss data is set 0x04 input control register 0x00 r/w input control register fo r out-of-standard quality input signal 0x05 device id & revision id register 0x17 r register for device id and revision id
asahi kasei [ak8817/18] rev.001e 40 2009 / 12 control 1 register (r/w) [address 0x00] sub address 0x00 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dac bbg cbg masmd wss vbid scr vmod default value 0 0 0 0 0 0 0 0 control 1 register definition bit register name r/w definition bit 0 vmod video mode bit r/w 0: ntsc 1: pal bit 1 scr sub-carrier reset bit r/w 0 : sub-carrier reset 1 : sub-carrier reset off bit 2 vbid vbid set bit r/w 0 : vbid off 1 : vbid on bit 3 wss wss set bit r/w 0 : wss off 1 : wss on bit 4 masmd master mode bit r/w master mode bit to set sync mode when color bar signal and black burst signal are generated 0 : operation by an external sync timing 1 : operation by an internal se lf-operating mode ( master mode ) note ) master mode bit is still valid in normal data input, but output video is not synchronized. bit 5 cbg color bar generator bit r/w 0: off 1: on when bbg is set, bbg is prioritized. bit 6 bbg black burst generator bit r/w 0 : off 1 : on bit 7 dac dac set bit r/w 0 : dac off 1 : dac on
asahi kasei [ak8817/18] rev.001e 41 2009 / 12 control 2 register (r/w) [address 0x01] sub address 0x01 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved vampmd1 vampmd0 setup rec656 pixrt default value 0 0 0 0 0 0 0 0 control 2 register definition bit register name r/w definition bit 0 pixrt pixel rate set bit r/w pixel rate setting is done. 0 : itu-r bt.601 data input ( at 27 mhz rate ) 1 : square pixel data input ntsc : 24.5454 mhz pal : 29.50 mhz bit 1 rec656 rec656 set bit r/w synchronization mode setting is done. 0 : synchronization is made with hdi / vdi input. 1 : synchronization is made with itu-r bt.656 data input bit 2 setup setup bit r/w set-up setting is done 0 : with no set-up 1 : with 7.5 ire set-up bit 3 ~ bit 4 vampmd0 ~ vampmd1 video amp mode set bit r/w operation mode for video amp. vampmd[1:0] 00: video amp off + sag compensation off 01: video amp on + sag compensation on 10: video amp on + no sag compensation 11: reserved bit 5 ~ bit 7 reserved reserved bit r/w set ?0?
asahi kasei [ak8817/18] rev.001e 42 2009 / 12 vbid/wss 1 register (r/w) [address 0x02] vbid/wss 2 register (r/w) [address 0x03] video id and wss data setting are made. a common data r egister is used for both video id and wss data. when vbid bit of mode register is set in ntsc mode, data is for vbid data ,and when wss bit of control 1 register is set in pal mode, data is for wss data. when vbid-bit is ?1? and vmod-bit is ?0? in control 1 register , the following bits are assigned. sub address 0x02 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbid7 vbid8 vbid9 vbid10 vbid11 vbid12 vbid13 vbid14 default value 0 0 0 0 0 0 0 0 sub address 0x03 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved vbid1 vbid2 vbid3 vbid4 vbid5 vbid6 default value 0 0 0 0 0 0 0 0 note ) ?0? should be written into reserved bits. vbid1 ---- vbid14 above correspond to the bit 1 ---- bit 14 whic h are described at { vbid data code assignment } in { ( 14 ) video id } section. a 6-bit crc code from bit 15 ~ bit 20 is automatically added by the ak8817/18. data is retained till data is updated to a new one. following bits are assigned when wss-bit is ?1? and vmod-bit is ?1? in control 1 register . sub address 0x02 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g2-7 g2-6 g2-5 g2-4 g1-3 g1-2 g1-1 g1-0 default value 0 0 0 0 0 0 0 0 sub address 0x03 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved g4-13 g412 g4-11 g3-10 g3-9 g3-8 default value 0 0 0 0 0 0 0 0 note ) wss data is written with 0x01 first, then 0x02 in this order. when the 2 nd byte ( 0x02 ) of wss data is wr itten, the ak8817/18 interprets that data is updated to a new one and then encodes it to the next video line ( line 23 ). data is retained till data is updated to a new one.
asahi kasei [ak8817/18] rev.001e 43 2009 / 12 input control register (r/w) [address 0x04] this is an out-of-standard quality input signal control register. sub address 0x04 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved cbcr vd2 vd1 vd0 hd2 hd1 hd0 0 0 0 0 0 0 0 0 adjustment of sync input timing is made. bit register name r/w definition bit 0 ~ bit 2 hd0 ~ hd2 hdi input delay r/w hdi signal input is delayed by the set value. hd [ 2:0 ] system clock count delay ( + 0 ~ + 7 clk delay ) bit 3 ~ bit 5 vd0 ~ vd2 vdi input delay r/w vdi signal input is delayed by the set value. vd [ 2:0 ] system clock count delay ( + 0 ~ + 7 clk delay ) bit 6 cbcr exchange cbcr r/w cb, cr ti ming data are interchanged at cbcr = 1. bit 7 reserved reserved r/w reserved
asahi kasei [ak8817/18] rev.001e 44 2009 / 12 device id and revision id register (r) [address 0x05] register to show device id & revision of the ak8817/18. device id for ak8817/18 is 0x17(decimal) initial version of the revision id is 0x00. revision number is modified only when a control software needs to be modified. sub address 0x5 default value 0x17 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev1 rev0 dev5 dev4 dev3 dev2 dev1 dev0 0 0 0 1 0 1 1 1 device id and revision id register definition bit register name r/w definition bit 0 ~ bit 5 dev0 ~ dev2 device id bit r to show device id device id is 0x17h. bit 6 ~ bit 7 rev0 ~ rev2 revision id bit r to show revision information revision id is updated when software modification is to be expected. it is 0x00.
asahi kasei [ak8817/18] rev.001e 45 2009 / 12 system connection example hsync vsync d[7:0] analog 3.0v 390 ohm dacout iref vref 0.1uf a vss 12k ohm avdd 0.1uf 10uf clkin test atpg dvss dvdd ak8817/18 vout sag 75 ohm clock clkin v i2c sda scl rstn pdn u - p pvd d pvss pvdd hdi vdi 47uf 1uf digital 3.0v avss dvss
asahi kasei [ak8817/18] rev.001e 46 2009 / 12 package drawing 41pin fbga 4.0 0.1 4.0 0.1 0.5 a b c e f g 7 6 5 3 2 41 - 0.3 0.05 0.08 s s 0.05 ab s b 0.5 m a 3.0 1.0max 0.25 0.05 4 d 3.0 1 package molding compound: epoxy interposer material: bt resin solder ball material: snagcu
asahi kasei [ak8817/18] rev.001e 47 2009 / 12 AK8817VQ / ak8818vq 48 lqfp 0.10 m 0.170.05 1.00 0.500.20 0.100.07 0.10 12 13 24 25 36 37 48 7.00 9.000.20 9.000.20 7.00 0.190.05 1 0.50 0 b 10b s s 1.4typ 1.60max
asahi kasei [ak8817/18] rev.001e 48 2009 / 12 package marking drawing ak8817vg / ak8818vg 8817 xxxx a. package type: bga b. number of pins: 41pi ns (including index pin ) c. product number: 8817 d. control code: xxxxx (4 digits) 8818 xxxx a. package type: bga b. number of pins: 41pi ns (including index pin ) c. product number: 8818 d. control code: xxxxx (4 digits)
asahi kasei [ak8817/18] rev.001e 49 2009 / 12 AK8817VQ / ak8818vq 1 a km AK8817VQ xxxxxxx akm: akm logo AK8817VQ: marketing code xxxxxxx (7 digits): date code 1 a km ak8818vq xxxxxxx akm: akm logo ak8818vq: marketing code xxxxxxx (7 digits): date code
asahi kasei [ak8817/18] rev.001e 50 2009 / 12 ? these products and their spec ifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co ., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, in tellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or dev ices or systems containing them, ma y require an export license or other official approval under the law and regulat ions of the country of export perta ining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility re lating to any such use, except with the express written consent of the representative direc tor of akm. as used here: (a) a hazard related device or system is one des igned or intended for life s upport or maintenance of safety or for applications in medici ne, aerospace, unclear ener gy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to f unction or perform may reasonably be expected to result, whether directly or indirectly, in the loss of t he safety or effectiveness of the device or system containing it, and which must t herefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who di stributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. important notice

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